`ifndef _ral_blk_Gjm_sys_global_cfg_rtl_
`define _ral_blk_Gjm_sys_global_cfg_rtl_

`include "vmm_ral_host_itf.sv"

`include "ral_reg_Gjm_sys_global_cfg_status_cfg_rtl.sv"


interface ral_blk_Gjm_sys_global_cfg_itf();

logic [3:0] intp_cfg_out;
logic intp_cfg_rd, intp_cfg_wr;
logic intp_cfg_wen;
logic [3:0] intp_cfg_in;
logic [27:0] rsvd_out;
logic rsvd_rd, rsvd_wr;
logic rsvd_wen;
logic [27:0] rsvd_in;


modport regs(output intp_cfg_out,
             output intp_cfg_rd,
             output intp_cfg_wr,
             input intp_cfg_wen,
             input intp_cfg_in,
             output rsvd_out,
             output rsvd_rd,
             output rsvd_wr,
             input rsvd_wen,
             input rsvd_in);


modport usr(input intp_cfg_out,
            input intp_cfg_rd,
            input intp_cfg_wr,
            output intp_cfg_wen,
            output intp_cfg_in,
            input rsvd_out,
            input rsvd_rd,
            input rsvd_wr,
            output rsvd_wen,
            output rsvd_in);

endinterface



module ral_blk_Gjm_sys_global_cfg_rtl(vmm_ral_host_itf.slave hst,
                                      ral_blk_Gjm_sys_global_cfg_itf.regs usr);
reg hst_ack;
assign hst.ack = hst_ack;
reg [3:0] status_cfg_sel;

always @(*)
   begin
      status_cfg_sel = 'b0;

      hst_ack = 0;

      if (hst.adr == 'h4) begin
         status_cfg_sel = hst.sel[3:0];
         hst_ack = hst.wen;
      end
   end


wire [31:0] status_cfg_out;
ral_reg_Gjm_sys_global_cfg_status_cfg_rtl status_cfg(hst.clk, hst.rstn,
                                                     hst.wdat[31:0], status_cfg_out, status_cfg_sel, hst.wen,
                                                     usr.intp_cfg_out,
                                                     usr.intp_cfg_rd,
                                                     usr.intp_cfg_wr,
                                                     usr.intp_cfg_wen,
                                                     usr.intp_cfg_in,
                                                     usr.rsvd_out,
                                                     usr.rsvd_rd,
                                                     usr.rsvd_wr,
                                                     usr.rsvd_wen,
                                                     usr.rsvd_in);


reg [31:0] _rdat;
always @(*)
   begin
      _rdat = 32'b0;
      unique casez ({|status_cfg_sel[3:0]})
         1'b1: _rdat = status_cfg_out;
         default: _rdat = 32'b0;
      endcase
   end
assign hst.rdat[31:0] = _rdat;

endmodule
`endif
